An issue in many types of analog to digital converters (ADCs) is nonlinear distortion introduced by non-ideal circuit elements. The performance of ADCs can be improved and the constraints on circuit elements be relaxed if the nonlinear distortion can be determined and corrected.
An example ADC in which nonlinear errors are of particular concern are in pipelined ADCs. Pipelined ADCs are widely used in applications that require data converters with resolutions in the range of 10 to 16 bits and bandwidths in the range of 15 to 250 MHz. For example, such applications include cellular telephone base station receivers, 802.11 wireless LAN receivers, and 802.16 wireless metropolitan area network receivers. More generally, pipelined ADCs are attractive when the required bandwidth is too high for oversampling delta-sigma ADCs to be efficient and the required resolution is too high for flash ADCs to be efficient.
The basic operation of a pipelined ADC has each stage reducing the error from each previous stage of the ADC. In a first stage, the input signal to be converted is converted with a flash ADC. The signal from the flash ADC is combined with the results from subsequent stages to form an output. The error in the initial stage is determined by converting the result of the flash ADC in that stage to a voltage with a digital to analog converter (DAC). The difference between the input signal to the stage and the signal from the DAC is the residue from the stage. The residue from each stage, except a final stage, is amplified by a residue amplifier and then converted in the same fashion in the next stage. The ADC in each stage is a coarse conversion, but the outputs of the stages are combined to eliminate most of the quantization noise from the coarse conversions in each stage. Each pipeline stage coarsely digitizes its input and passes amplified quantization noise to the next stage. Distortion introduced by the residue amplifiers, particularly those in the first few stages, results in imperfect quantization noise cancellation. This reduces the linearity of a pipelined ADC and increases its noise floor. For this reason, pipelined ADCs are particularly sensitive to distortion introduced by the residue amplifiers in their first few stages.
Residue amplifier distortion tends to be inversely related to power consumption. The residue amplifiers are often the dominant consumers of power in high-resolution pipelined ADCs. In order to achieve high accuracy, a pipelined ADC typically relies upon high-power, high-linearity residue amplifiers. If lower power consumption is required, the resulting accuracy of the pipelined ADC is significantly compromised in the conventional pipelined ADCs. Many applications could benefit from accurate, high resolution amplifiers that have reasonable power consumption.
A 15-bit, 40-MS/s pipelined ADC integrated circuit (IC) [described in “A Digitally Enhanced 1.8V 15b 40 MS/s CMOS Pipelined ADC,” E. Siragusa, I. Galton, IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, (2004).] provides a convenient circuit-level example of the issues described above. The ADC is based on the architecture shown in FIGS. 1A and 1B, but modified to include digital background calibration techniques that cancel ADC error arising from DAC capacitor mismatches and interstage gain errors. The ADC achieves over 90 dB of spurious-free dynamic range (SFDR) and 72 dB of peak signal-to-noise-and-distortion ratio (SNDR) over the 20 MHz bandwidth. To achieve sufficiently low distortion for this level of ADC performance, high-power residue amplifiers are used in the design: the op-amps in the residue amplifiers consume approximately 80% of the 400 mW consumed by the entire IC.
Had the sample-rate been higher than 40 MHz, even higher-performance, and, therefore, higher-power, residue amplifiers would have been required to maintain the same SFDR and peak SNDR. For example, circuit simulations indicate that the pipelined ADCs SFDR and peak SNDR drop to 65 dB and 56 dB, respectively if the sample-rate is increased to 100 MHz without improving the performance of the residue amplifiers. Simulation of the residue amplifier stage indicates that this reduction in performance comes from both linear gain error associated with incomplete settling and from third order distortion. The use of differential circuitry causes the even-order terms to be negligible in this example relative to the target specifications of 90 dB SFDR and 72 dB peak SNDR, and, although higher-order distortion terms are present, they too are negligible in this example.
Pipelined ADCs have been proposed with nonlinear error correction. Examples include B. Murmann, B. Boser, “A 12b 75 MS/s Pipelined ADC using Open-Loop Residue Amplification,” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, December 2003; J. P. Keane, P. J. Hurst, S. H. Lewis, “Background Interstage Gain Calibration Technique for Pipelined ADCs,” IEEE Transactions on Circuits and Systems I, vol. 52, no. 1, pp. 32-43, January 2005.